Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests

Rimantas Seinauskas

doi:doi:10.11648/j.cssp.20160502.11

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Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests

Rimantas Seinauskas

Published in Science Journal of Circuits, Systems and Signal Processing (Volume 5, Issue 2)

Received: 15 August 2016 Accepted: 23 August 2016 Published: 9 September 2016

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Abstract

At speed delay testing is important for embedded systems. Attempts to solve the problems of delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to oppose these tests, but it is necessary to use both taking full advantage of their opportunities. Design flow and the ability to use non-scan and scan-based ATPG, functional test and fault simulation is presented. The goal is to detect as many faults with non-scan at-speed test. The remaining faults are detected with a scan-based test. As a result, there are less of undetected faults and the length of the scan-based test is reduced. The proposed approach provides more flexibility for test generation. Design flow forced the development of new methods for speeding up fault simulation and for more efficient generation of input patterns. Experimental results demonstrate the possibilities of approach.

Published in	Science Journal of Circuits, Systems and Signal Processing (Volume 5, Issue 2)
DOI	10.11648/j.cssp.20160502.11
Page(s)	8-18
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2016. Published by Science Publishing Group

Keywords

Non-scan Test, Scan-Based Test, Functional Test, Design Flow

References

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Rimantas Seinauskas. (2016). Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests. Science Journal of Circuits, Systems and Signal Processing, 5(2), 8-18. https://doi.org/10.11648/j.cssp.20160502.11

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ACS Style

Rimantas Seinauskas. Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests. Sci. J. Circuits Syst. Signal Process. 2016, 5(2), 8-18. doi: 10.11648/j.cssp.20160502.11

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AMA Style

Rimantas Seinauskas. Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests. Sci J Circuits Syst Signal Process. 2016;5(2):8-18. doi: 10.11648/j.cssp.20160502.11

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@article{10.11648/j.cssp.20160502.11,
  author = {Rimantas Seinauskas},
  title = {Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests},
  journal = {Science Journal of Circuits, Systems and Signal Processing},
  volume = {5},
  number = {2},
  pages = {8-18},
  doi = {10.11648/j.cssp.20160502.11},
  url = {https://doi.org/10.11648/j.cssp.20160502.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20160502.11},
  abstract = {At speed delay testing is important for embedded systems. Attempts to solve the problems of delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to oppose these tests, but it is necessary to use both taking full advantage of their opportunities. Design flow and the ability to use non-scan and scan-based ATPG, functional test and fault simulation is presented. The goal is to detect as many faults with non-scan at-speed test. The remaining faults are detected with a scan-based test. As a result, there are less of undetected faults and the length of the scan-based test is reduced. The proposed approach provides more flexibility for test generation. Design flow forced the development of new methods for speeding up fault simulation and for more efficient generation of input patterns. Experimental results demonstrate the possibilities of approach.},
 year = {2016}
}

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TY  - JOUR
T1  - Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests
AU  - Rimantas Seinauskas
Y1  - 2016/09/09
PY  - 2016
N1  - https://doi.org/10.11648/j.cssp.20160502.11
DO  - 10.11648/j.cssp.20160502.11
T2  - Science Journal of Circuits, Systems and Signal Processing
JF  - Science Journal of Circuits, Systems and Signal Processing
JO  - Science Journal of Circuits, Systems and Signal Processing
SP  - 8
EP  - 18
PB  - Science Publishing Group
SN  - 2326-9073
UR  - https://doi.org/10.11648/j.cssp.20160502.11
AB  - At speed delay testing is important for embedded systems. Attempts to solve the problems of delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to oppose these tests, but it is necessary to use both taking full advantage of their opportunities. Design flow and the ability to use non-scan and scan-based ATPG, functional test and fault simulation is presented. The goal is to detect as many faults with non-scan at-speed test. The remaining faults are detected with a scan-based test. As a result, there are less of undetected faults and the length of the scan-based test is reduced. The proposed approach provides more flexibility for test generation. Design flow forced the development of new methods for speeding up fault simulation and for more efficient generation of input patterns. Experimental results demonstrate the possibilities of approach.
VL  - 5
IS  - 2
ER  -

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Author Information

Rimantas Seinauskas

Software Department, Informatic Faculty, Kaunas University of Technology, Kaunas, Lithuania

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APA Style

Rimantas Seinauskas. (2016). Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests. Science Journal of Circuits, Systems and Signal Processing, 5(2), 8-18. https://doi.org/10.11648/j.cssp.20160502.11

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ACS Style

Rimantas Seinauskas. Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests. Sci. J. Circuits Syst. Signal Process. 2016, 5(2), 8-18. doi: 10.11648/j.cssp.20160502.11

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AMA Style

Rimantas Seinauskas. Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests. Sci J Circuits Syst Signal Process. 2016;5(2):8-18. doi: 10.11648/j.cssp.20160502.11

Copy | Download

@article{10.11648/j.cssp.20160502.11,
  author = {Rimantas Seinauskas},
  title = {Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests},
  journal = {Science Journal of Circuits, Systems and Signal Processing},
  volume = {5},
  number = {2},
  pages = {8-18},
  doi = {10.11648/j.cssp.20160502.11},
  url = {https://doi.org/10.11648/j.cssp.20160502.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20160502.11},
  abstract = {At speed delay testing is important for embedded systems. Attempts to solve the problems of delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to oppose these tests, but it is necessary to use both taking full advantage of their opportunities. Design flow and the ability to use non-scan and scan-based ATPG, functional test and fault simulation is presented. The goal is to detect as many faults with non-scan at-speed test. The remaining faults are detected with a scan-based test. As a result, there are less of undetected faults and the length of the scan-based test is reduced. The proposed approach provides more flexibility for test generation. Design flow forced the development of new methods for speeding up fault simulation and for more efficient generation of input patterns. Experimental results demonstrate the possibilities of approach.},
 year = {2016}
}

Copy | Download

TY  - JOUR
T1  - Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests
AU  - Rimantas Seinauskas
Y1  - 2016/09/09
PY  - 2016
N1  - https://doi.org/10.11648/j.cssp.20160502.11
DO  - 10.11648/j.cssp.20160502.11
T2  - Science Journal of Circuits, Systems and Signal Processing
JF  - Science Journal of Circuits, Systems and Signal Processing
JO  - Science Journal of Circuits, Systems and Signal Processing
SP  - 8
EP  - 18
PB  - Science Publishing Group
SN  - 2326-9073
UR  - https://doi.org/10.11648/j.cssp.20160502.11
AB  - At speed delay testing is important for embedded systems. Attempts to solve the problems of delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to oppose these tests, but it is necessary to use both taking full advantage of their opportunities. Design flow and the ability to use non-scan and scan-based ATPG, functional test and fault simulation is presented. The goal is to detect as many faults with non-scan at-speed test. The remaining faults are detected with a scan-based test. As a result, there are less of undetected faults and the length of the scan-based test is reduced. The proposed approach provides more flexibility for test generation. Design flow forced the development of new methods for speeding up fault simulation and for more efficient generation of input patterns. Experimental results demonstrate the possibilities of approach.
VL  - 5
IS  - 2
ER  -

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